// Cell names have been changed in this file by netl_namemap on Mon Jan  3 04:00:05 UTC 2022
////////////////////////////////////////////////////////////////////////////// 
//
//  ani_tech_cells.v
//
//  Generic cells for synthesis use to replace specific foundry cells.
//
//  Original Author: Richard Steeves
//  Current Owner:   Richard Steeves
//
////////////////////////////////////////////////////////////////////////////// 
//
// Copyright (C) 2007 Synopsys, Inc.  All rights reserved.
//
// SYNOPSYS CONFIDENTIAL - This is an unpublished, proprietary work of
// Synopsys, Inc., and is fully protected under copyright and trade secret
// laws.  You may not view, use, disclose, copy, or distribute this file or
// any information contained herein except pursuant to a valid written
// license agreement. It may not be used, reproduced, or disclosed to others
// except in accordance with the terms and conditions of that agreement.
//
////////////////////////////////////////////////////////////////////////////// 
//
//  Perfoce Information:
//   $Author: achao $
//   $File: //dwh/up16/main/dev/pma/include/ani_techcell_lib.v $
//   $DateTime: 2015/04/27 12:22:06 $
//   $Revision: #3 $
//
////////////////////////////////////////////////////////////////////////////// 


`ifdef ANI_TECH_CELL_V
`else

`define ANI_TECH_CELL_V

module dwc_e12mp_phy_x4_ns_ani_buf (
input  A,
output Y
);

// assign Y = A;
BUFH_X1M_A12PP140ZTS_C35 U1 (.A(A),.Y(Y));

endmodule // ani_buf


module dwc_e12mp_phy_x4_ns_ani_clk_gate (
input  CK,
input  E,
input  SE,
output ECK
);

// reg en_f;
// always @(CK or SE or E) begin
//   if (!CK)
//     en_f <= SE || E;
// end
// assign ECK = en_f & CK;
PREICG_X1B_A12PP140ZTS_C35 U1 (.CK(CK), .E(E), .SE(SE), .ECK(ECK));

endmodule // ani_clk_gate


module dwc_e12mp_phy_x4_ns_ani_clk_mux (
input  A,
input  B,
input  S0,
output Y
);

// assign Y = S0 ? B : A;
MXGL2_X1B_A12PP140ZTS_C35 U1 (.A(A), .B(B), .S0(S0), .Y(Y));

endmodule // ani_clk_mux


module dwc_e12mp_phy_x4_ns_ani_clk_and2 (
input  A,
input  B,
output Y
);

// assign Y = (A & B);
AND2_X1B_A12PP140ZTS_C35 U1 (.A(A), .B(B), .Y(Y));

endmodule // ani_clk_and2


module dwc_e12mp_phy_x4_ns_ani_clk_and3 (
input  A,
input  B,
input  C,
output Y
);

// assign Y = (A & B & C);
AND3_X1M_A12PP140ZTS_C35 U1 (.A(A), .B(B), .C(C), .Y(Y));

endmodule // ani_clk_and3


module dwc_e12mp_phy_x4_ns_ani_clk_or2 (
input  A,
input  B,
output Y
);

// assign Y = (A | B);
OR2_X1B_A12PP140ZTS_C35 U1 (.A(A), .B(B), .Y(Y));

endmodule // ani_clk_or2


module dwc_e12mp_phy_x4_ns_ani_mux (
input  A,
input  B,
input  S0,
output Y
);

// assign Y = S0 ? B : A;
MXGL2_X1B_A12PP140ZTS_C35 U1 (.A(A), .B(B), .S0(S0), .Y(Y));

endmodule // ani_clk_mux

`endif

